
/**
 * @note : n选1 的 多路选择器
 * 
 * 
 * 
 */ 
module mux_t #(
	parameter SEL_NUM = 3 , 
	parameter SEL_WD  = 2 , //sel signal width 
	parameter DATA_WD = 4 ,//data_width 
	parameter DEFAULT = 'd0 
	)(
		input  wire  [SEL_WD - 1 : 0] sel ,
		output logic [DATA_WD-1:0] data_o ,
		
		input  wire  [(SEL_WD + DATA_WD )*3 -1 : 0 ] sel_and_data_in 		
	) ;

	logic [SEL_WD - 1  : 0 ] sel_array [0:SEL_NUM - 1 ];
	logic [DATA_WD- 1  : 0 ] data_array[0:SEL_NUM - 1 ];
	logic [DATA_WD+SEL_WD -1 : 0 ] sel_and_data_array [0 : SEL_NUM - 1 ];

	genvar i ;
	generate
		for(i=0 ;i<SEL_NUM;i++)begin :sel_a_gen
			assign sel_and_data_array[i] = sel_and_data_in[(SEL_WD+DATA_WD)*(i+1)-1-:(SEL_WD+DATA_WD)];
			assign sel_array[i] = sel_and_data_array[i][SEL_WD+DATA_WD-1-:SEL_WD];
			assign data_array[i] = sel_and_data_array[i][DATA_WD-1-:DATA_WD];
		end
	endgenerate

	logic hit ;
	logic [DATA_WD-1:0] data_o_tmp ;
	always_comb begin
		hit = 0 ;
		data_o_tmp = {DATA_WD{1'b0}} ;

		for(int idx = 0 ;idx <SEL_NUM ;idx++)begin : sel_data_hit
			data_o_tmp = data_o_tmp | ({DATA_WD{sel_array[idx] == sel }} & data_array[idx]) ;
			hit = hit | (sel_array[idx] == sel ) ;
		end
		if(!DEFAULT) data_o = data_o_tmp ;
		data_o = (hit) ? data_o_tmp : DEFAULT ;
	end
	
endmodule:mux_t